The 5P35021 is a VersaClock programmable clock generator and is designed for low power, consumer, and high performance PCI Express applications. The 5P35021 device is a three PLL architecture design, and each PLL is individually programmable and allowing for up to five unique frequency outputs. The 5P35021 has built-in unique features such as Proactive Power Saving (PPS), Performance-Power Balancing (PPB), Overshot Reduction Technology (ORT) and Extreme Low Power DCO. An internal OTP memory allows the user to store the configuration in the device without programming after power up, then program the 5P35021 again through the I2C interface.
 
The device has programmable VCO and PLL source selection to allow the user to do power-performance optimization based on the application requirements. It also supports one single-ended output and two pair of differential outputs that support LVCMOS, LVPECL, LVDS and LPHCSL. A Low Power 32.768kHz clock is supported with only less than 5μA current consumption for system RTC reference clock.
 

Features

  • Configurable OE pin function as OE, PD#, PPS or DFC control function
  • Configurable PLL bandwidth/minimizes jitter peaking
  • PPS: Proactive Power Saving features save power during the end device power down mode
  • PPB: Performance- Power Balancing feature allows minimum power consumption base on required performance
  • DFC: Dynamic Frequency Control feature allows up to 4 difference frequencies switch dynamically
  • Spread Spectrum clock support to lower system EMI
  • I2C interface
  • Also supports crystal input
  • Available in AEC-Q100 qualified, Grade 2 (-40°C to +105°C) version

Product Options

This device is factory-configurable. Try the Custom Part Configuration Utility.
下单器件 ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Temp. Range Carrier Type Buy Sample
5P35021-000NDGI Active NDG20P2 VFQFPN 20 I -40 to 85°C Tray
Availability
5P35021-000NDGI8 Active NDG20P2 VFQFPN 20 I -40 to 85°C Reel
Availability
5P35021-000NDG2 Active NDG20S1 VFQFPN 20 2 -40 to 105°C Tray
Availability
5P35021-000NDG28 Active NDG20S1 VFQFPN 20 2 -40 to 105°C Reel
Availability

Product Comparison

5P35021 5L35021 5L35023 5P35023
Outputs (#) 5 5 7 7
Output Type HCSL, LVCMOS, LVDS, LVPECL LP-HCSL, LVCMOS LP-HCSL, LVCMOS LP-HCSL, LVCMOS, LVDS, LVPECL
Core Voltage (V) 3.3 1.8 1.8 3.3
Output Voltage (V) 1.8, 2.5, 3.3 1.8 1.8 1.8, 2.5, 3.3
Pkg. Dimensions (mm) 3.0 x 3.0 x 1.0 3.0 x 3.0 x 1.0 4.0 x 4.0 x 0.9 4.0 x 4.0 x 0.9

技术资料

文档标题 他の言語 文档类型 文档格式 文件大小
数据手册与勘误表
5P35021 Datasheet Datasheet PDF 540 KB
使用指南与说明
VersaClock 3S - 5P3502x Family Programmer Board User Guide Manual PDF 1.18 MB
Timing Commander Installation Guide Guide PDF 497 KB
应用指南 &白皮书
AN-960 Layout and EMI Recommendations for Automotive Applications (short form) Application Note PDF 200 KB
AN-954 Layout and EMI Recommendations for Automotive Applications Application Note PDF 271 KB
AN-909 PCB Layout Considerations for Designing IDT VersaClock 3S, 5 and 6 Clock Products Application Note PDF 743 KB
AN-918 Programmable Clocks vs Crystal Oscillators Application Note PDF 221 KB
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT's "Universal" Low-Power HCSL Outputs Application Note PDF 354 KB
AN-846 Termination - LVDS Application Note PDF 50 KB
AN-845 Termination - LVCMOS Application Note PDF 62 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB
AN-815 Understanding Jitter Units Application Note PDF 476 KB
AN-806 Power Supply Noise Rejection Application Note PDF 353 KB
AN-808 PCI Express/HCSL Termination Application Note PDF 54 KB
PCN / PDN
PCN# : A1611-02 Add JCET China as Alternate Assembly and Change of Material Set at Alternate Assembly Location Product Change Notice PDF 583 KB
其它
VersaClock Family Overview 日本語 Overview PDF 803 KB
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Products for Radio Applications 日本語 Product Brief PDF 2.34 MB
5P35021 Reference Schematic Schematic PDF 20 KB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB
IDT Clocks for Altera's Stratix V and Arria V/X FPGAs Technical Brief PDF 238 KB

软件与工具

文档标题 他の言語 文档类型 文档格式 文件大小
Timing Commander Installer (v1.15.0.27471) Software ZIP 19.57 MB
VersaClock 3S Timing Commander Personality File Software TCP 5.00 MB
Timing Commander Software for VersaClock 3S - 5P3502x Manual - Software PDF 1.55 MB
5P35021 IBIS Model Model - IBIS ZIP 74 KB

Evaluation Boards

Part Number Title 升序排列
EVK5P35021 Evaluation Board for 5P35021 VersaClock 3S
DEV5P35021 5P35021 VersaClock 3S Programmable Clock Development Kit