NOTICE - The following device(s) are recommended alternatives:

The 873995 is a Zero Delay/Multiplier/Divider with hitless input clock switching capability. The 873995 is ideal for use in redundant, fault tolerant clock trees where low phase noise and low jitter are critical. The device receives two differential LVPECL clock signals from which it generates 6 LVPECL clock outputs with "zero" delay. The output divider and feedback divider selections also allow for frequency multiplication or division. The 873995 Dynamic Clock Switch (DCS) circuit continuously monitors both input clock signals. Upon detection of a failure (input clock stuck LOW or HIGH for at least 1 period), INP_BAD for that clock will be set HIGH. If that clock is the primary clock, the DCS will switch to the good secondary clock and phase/frequency alignment will occur with minimal output phase disturbance. The low jitter characteristics combined with input clock monitoring and automatic switching from bad to good input clocks make the 873995 an ideal choice for mission critical applications that utilize 1G or 10G Ethernet or 1G/4G/10G Fibre Channel.


  • Six differential 3.3V LVPECL outputs
  • Selectable differential clock inputs
  • CLKx, nCLKx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
  • Input clock frequency range: 49MHz to 213.33MHz
  • Output clock frequency range: 49MHz to 640MHz
  • VCO range: 490MHz to 640MHz
  • External feedback for "zero delay" clock regeneration with configurable frequencies
  • Output skew: 100ps (maximum)
  • RMS phase jitter (1.875MHz - 20MHz): 0.77ps (typical) assuming a low phase noise reference clock input
  • 3.3V supply voltage
  • 0°C to 70°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

Product Options

下单器件 ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
873995AYLF Obsolete DXG48 PTQFP 48 C Yes Tray
873995AYLFT Obsolete DXG48 PTQFP 48 C Yes Reel


文档标题 他の言語 文档类型 文档格式 文件大小
873995 Datasheet Datasheet PDF 307 KB
应用指南 &白皮书
AN-828 Termination - LVPECL Application Note PDF 229 KB
AN-831 The Crystal Load curve Application Note PDF 308 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB
AN-803 Crystal Timing Budget and Accuracy for IDT Timing Clock Products Application Note PDF 44 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB
AN-839 RMS Phase Jitter Application Note PDF 149 KB
AN-838 Peak-to-Peak Jitter Calculations Application Note PDF 32 KB
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB
AN-832 Timing Budget and Accuracy Application Note PDF 48 KB
AN-830 Quartz Crystal Drive Level Application Note PDF 59 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB
AN-815 Understanding Jitter Units Application Note PDF 476 KB
AN-802 Crystal-Measuring Oscillator Negative Resistance Application Note PDF 52 KB
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB
AN-801 Crystal-High Drive Level Application Note PDF 109 KB
AN-806 Power Supply Noise Rejection Application Note PDF 353 KB
PDN# : CQ-15-04 Quarterly Market Declined PDN Product Discontinuation Notice PDF 545 KB
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Products for Radio Applications 日本語 Product Brief PDF 2.34 MB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB


文档标题 他の言語 文档类型 文档格式 文件大小
873995 IBIS Model Model - IBIS ZIP 58 KB