The 8430S10I-03 is a PLL-based clock generator specifically designed for Cavium Networks SoC processors. This high performance device is optimized to generate the processor core reference clock, the DDR reference clocks, the PCI/PCI-X bus clocks, and the clocks for both the Gigabit Ethernet MAC and PHY. The clock generator offers low-jitter, low-skew clock outputs, and edge rates that easily meet the input requirements for the CN30XX/CN31XX/CN38XX/CN58XX processors. The output frequencies are generated from a 25MHz external input source or an external 25MHz parallel resonant crystal. The extended temperature range of the 8430S10I-03 supports telecommunication, networking, and storage requirements.

Features

  • One selectable differential output pair for DDR 533/400/667, LVPECL, LVDS interface levels
  • Nine LVCMOS/ LVTTL outputs, 23Ω typical output impedance
  • Selectable external crystal or differential input source
  • Crystal oscillator interface designed for 25MHz, parallel resonant crystal
  • Differential input pair (PCLK, nPCLK) accepts LVPECL, LVDS, CML, SSTL input levels
  • Internal resistor bias on nPCLK pin allows the user to drive PCLK input with external single-ended (LVCMOS/ LVTTL) input levels
  • Power supply modes: CORE / OUTPUT 3.3V / 3.3V LVDS, LVPECL, LVCMOS 3.3V / 2.5V LVCMOS
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

Product Options

下单器件 ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
8430S10BYI-03LF Active DXG48P2 PTQFP 48 I Yes Tray
Availability
8430S10BYI-03LFT Active DXG48P2 PTQFP 48 I Yes Reel
Availability

技术资料

文档标题 他の言語 文档类型 文档格式 文件大小
数据手册与勘误表
ICS8430S10I-03 DATASHEET Datasheet PDF 559 KB
应用指南 &白皮书
AN-828 Termination - LVPECL Application Note PDF 229 KB
AN-831 The Crystal Load curve Application Note PDF 308 KB
AN-846 Termination - LVDS Application Note PDF 50 KB
AN-845 Termination - LVCMOS Application Note PDF 62 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB
AN-803 Crystal Timing Budget and Accuracy for IDT Timing Clock Products Application Note PDF 44 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB
AN-839 RMS Phase Jitter Application Note PDF 149 KB
AN-838 Peak-to-Peak Jitter Calculations Application Note PDF 32 KB
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB
AN-837 Overdriving the Crystal Interface Application Note PDF 50 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB
AN-832 Timing Budget and Accuracy Application Note PDF 48 KB
AN-830 Quartz Crystal Drive Level Application Note PDF 59 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB
AN-815 Understanding Jitter Units Application Note PDF 476 KB
AN-802 Crystal-Measuring Oscillator Negative Resistance Application Note PDF 52 KB
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB
AN-801 Crystal-High Drive Level Application Note PDF 109 KB
AN-806 Power Supply Noise Rejection Application Note PDF 353 KB
PCN / PDN
PCN# : A1709-02 Add alternate assembly at OSET and Convert to Copper Wire Product Change Notice PDF 35 KB
PCN# : A1402-02 Alternate Assembly Locations Product Change Notice PDF 34 KB
其它
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Products for Radio Applications 日本語 Product Brief PDF 2.34 MB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB