NOTICE - The following device(s) are recommended alternatives:

The MPC962309 has two banks of four outputs each, which can be controlled by the Select Inputs as shown in Table 3. Bank B can be tri-stated if all of the outputs are not required. Select inputs also allow the input clock to be directly applied to the outputs for chip and system testing purposes. The MPC962305 and MPC962309 PLLs enters a power down state when there are no rising edges on the REF input. During this state, all of the outputs are in tristate, the PLL is turned off, and there is less than 25.0 ?A of current draw for the device. The PLL shuts down in one additional case as shown in Table 3. Multiple MPC962305 and MPC962309 devices can accept the same input clock and distribute it throughout the system. In this situation, the difference between the output skews of two devices will be less than 700 ps. All outputs have less than 200 ps of cycle-cycle jitter. The input-to-output propagation delay on both devices is guaranteed to be less than 350 ps and the output-to-output skew is guaranteed to be less than 250 ps. The MPC962305 and MPC962309 are available in two/three different configurations, as shown on the ordering information page. The MPC962305-1/MPC962309-1 are the base parts. High drive versions of those devices, MPC962305-1H and MPC962309-1H, are available to provide faster rise and fall times of the base device.

Features

  • 1:5 LVCMOS zero-delay buffer (MPC962305)
  • 1:9 LVCMOS zero-delay buffer (MPC962309)
  • Zero input-output propagation delay
  • Multiple low-skew outputs
  • 250 ps max output-output skew
  • 700 ps max device-device skew
  • Supports a clock I/O frequency range of 10 MHz to 133 MHz, compatible with CPU and PCI bus frequencies
  • Low jitter, 200 ps max cycle-cycle, and compatible with Pentium® based systems
  • Test Mode to bypass PLL (MPC962309 only. See Table 3)
  • 8-pin SOIC or 8-pin TSSOP package (MPC962305)
  • 16-pin SOIC or 16-pin TSSOP package (MPC962309)
  • Single 3.3 V supply
  • Ambient temperature range: –40°C to +85°C
  • Compatible with the CY2305, CY23S05, CY2309, CY23S09
  • Spread spectrum compatible
  • Pb-free packages available

Product Options

下单器件 ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
MPC962305EF-1H Obsolete DCG8 SOIC 8 C Yes Tube
Availability
MPC962305EF-1HR2 Obsolete DCG8 SOIC 8 C Yes Reel
Availability
MPC962305EJ-1H Obsolete PGG8 TSSOP 8 C Yes Tube
Availability
MPC962305EJ-1HR2 Obsolete PGG8 TSSOP 8 C Yes Reel
Availability

技术资料

文档标题 他の言語 文档类型 文档格式 文件大小
数据手册与勘误表
MPC962305 Datasheet Datasheet PDF 259 KB
应用指南 &白皮书
AN-828 Termination - LVPECL Application Note PDF 229 KB
AN-845 Termination - LVCMOS Application Note PDF 62 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB
AN-815 Understanding Jitter Units Application Note PDF 476 KB
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB
PCN / PDN
PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB
PDN#: N-16-02 PRODUCT DISCONTINUANCE NOTICE ON SELECT DEVICES Product Discontinuation Notice PDF 161 KB
PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB
PDN# : N-12-48 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 93 KB
其它
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB

软件与工具

文档标题 他の言語 文档类型 文档格式 文件大小
MPC962305 IBIS Model Model - IBIS ZIP 27 KB