The 8761I is a low voltage, low skew PCI / PCI-X clock generator. The 8761I has a selectable REF_CLK or crystal input. The REF_CLK input accepts LVCMOS or LVTTL input levels. The 8761I has a fully integrated PLL along with frequency configurable clock and feedback outputs for multiplying and regenerating clocks with "zero delay". Using a 20MHz or 25MHz crystal or a 33.333MHz or 66.666MHz reference frequency, the 8761I will generate output frequencies of 33.333MHz, 66.666MHz, 100MHz and 133.333MHz simultaneously. The low impedance LVCMOS/LVTTL outputs of the 8761I are designed to drive 50Ω series or parallel terminated transmission lines.

Features

  • Fully integrated PLL
  • Seventeen LVCMOS/LVTTL outputs, 15Ω typical output impedance
  • Selectable crystal oscillator interface or LVCMOS/LVTTL REF_CLK
  • Maximum output frequency: 166.67MHz
  • Maximum crystal input frequency: 40MHz
  • Maximum REF_CLK input frequency: 83.33MHz
  • Individual banks with selectable output dividers for generating 33.333MHz, 66.66MHz, 100MHz and 133.333MHz simultaneously
  • Separate feedback control for generating PCI / PCI-X frequencies from a 20MHz or 25MHz crystal or 33.333MHz or 66.666MHz reference frequency
  • Cycle-to-cycle jitter: 70ps (maximum)
  • Period jitter, RMS: 17ps (maximum)
  • Output skew: 250ps (maximum)
  • Bank skew: 50ps (maximum)
  • Static phase offset: 0 ± 150ps (maximum)
  • Full 3.3V or 3.3V core, 2.5V multiple output supply modes
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free RoHS-compliant package

Product Options

下单器件 ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
8761CYILF Last Time Buy PPG64 TQFP 64 I Yes Tray
Availability
8761CYILFT Last Time Buy PPG64 TQFP 64 I Yes Reel
Availability

技术资料

文档标题 他の言語 文档类型 文档格式 文件大小
数据手册与勘误表
8761i Datasheet Datasheet PDF 480 KB
应用指南 &白皮书
AN-828 Termination - LVPECL Application Note PDF 229 KB
AN-845 Termination - LVCMOS Application Note PDF 62 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB
AN-815 Understanding Jitter Units Application Note PDF 476 KB
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB
PCN / PDN
PDN# : CQ-19-01 Quarterly Market Declined PDN Product Discontinuation Notice PDF 537 KB
PDN# : CQ-16-04 QUARTER MARKET DECLINED PDN Product Discontinuation Notice PDF 560 KB
PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB
PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB
PDN# : N-12-22R2 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 363 KB
PDN# : N-12-22R1 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 209 KB
其它
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB

软件与工具

文档标题 他の言語 文档类型 文档格式 文件大小
8761I IBIS Model Model - IBIS ZIP 67 KB