The 8T53S111I is a high-performance differential LVPECL fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8T53S111I is characterized to operate from a 3.3V and 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8T53S111I ideal for those clock distribution applications demanding well-defined performance and repeatability. Two selectable differential inputs and ten low skew outputs are available. The integrated VREF voltage generator enables easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise.

Features

  • Ten low skew, low additive jitter LVPECL outputs
  • Two selectable, differential LVPECL clock inputs
  • Differential pairs can accept the following differential input levels: LVDS and LVPECL
  • Maximum input clock frequency: 2.5GHz
  • LVCMOS interface levels for the control input (input select)
  • Output skew: 15ps (typical)
  • Propagation delay: 250ps (typical)
  • Additive phase jitter, RMS
  • fREF = 155.52MHz (12kHz - 20MHz): 77fs (typical)
  • Full 3.3V and 2.5V supply voltage
  • Maximum device current consumption (IEE): 100mA (typical)
  • Lead-free (RoHS 6) 32-Lead VFQFN package
  • -40°C to 85°C ambient operating temperature

Product Options

下单器件 ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
8T53S111NLGI Active NLG32P1 VFQFPN 32 I Yes Tray
Availability
8T53S111NLGI8 Active NLG32P1 VFQFPN 32 I Yes Reel
Availability

技术资料

文档标题 他の言語 文档类型 文档格式 文件大小
数据手册与勘误表
8T53S111I Data Sheet Datasheet PDF 496 KB
应用指南 &白皮书
AN-828 Termination - LVPECL Application Note PDF 229 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB
AN-815 Understanding Jitter Units Application Note PDF 476 KB
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB
PCN / PDN
PCN# : A1611-02 Add JCET China as Alternate Assembly and Change of Material Set at Alternate Assembly Location Product Change Notice PDF 583 KB
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB
其它
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB