The 8T39S04A is a high-performance clock fanout buffer. The input clock can be selected from two differential inputs or one crystal input. The internal oscillator circuit is automatically disabled if the crystal input is not selected. The crystal pin can be driven by a single-ended clock.The selected signal is distributed to four differential outputs which can be configured as LVPECL, LVDS or HSCL outputs. In addition, an LVCMOS output is provided. All outputs can be disabled into a high-impedance state. The device is designed for a signal fanout of high-frequency, low phase-noise clock and data signal. The outputs are at a defined level when inputs are open or tied to ground. It is designed to operate from a 3.3V or 2.5V core power supply, and either a 3.3V or 2.5V output operating supply.

Features

  • Two differential reference clock input pairs
  • Differential input pairs can accept the following input levels:
    LVPECL, LVDS, HCSL, HSTL and Single-ended
  • Crystal Oscillator Interface
  • Crystal input frequency range: 10MHz to 40MHz
  • Maximum Output Frequency
    LVPECL - 2GHz
    LVDS - 2GHz
    HCSL - 250MHz
    LVCMOS - 250MHz
  • Two banks, each has two differential output pairs that can be
    configured as LVPECL or LVDS or HCSL
  • One single-ended reference output with synchronous enable to
    avoid clock glitch
  • Output skew: 80ps (maximum), Bank A and Bank B at the same
    output level
  • Part-to-part skew: 200ps (typical), design target
  • Additive RMS phase jitter @ 156.25MHz, (12kHz - 20MHz):
    34.7fs (typical), 3.3V/ 3.3V
  • Supply voltage modes:
    VDD/VDDO
    3.3V/3.3V
    3.3V/2.5V
    2.5V/2.5V
  • -40°C to 85°C ambient operating temperature
  • Lead-free (RoHS 6) packaging

Product Options

下单器件 ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
8T39S04ANBGI Active NBG32P1 VFQFPN 32 I Yes Tray
Availability
8T39S04ANBGI8 Active NBG32P1 VFQFPN 32 I Yes Reel
Availability

技术资料

文档标题 他の言語 文档类型 文档格式 文件大小
数据手册与勘误表
8T39S04A Datasheet Datasheet PDF 912 KB
应用指南 &白皮书
AN-828 Termination - LVPECL Application Note PDF 229 KB
AN-846 Termination - LVDS Application Note PDF 50 KB
AN-845 Termination - LVCMOS Application Note PDF 62 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB
AN-815 Understanding Jitter Units Application Note PDF 476 KB
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB
其它
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB