The 889474 is a high speed 2-to-1 differential multiplexer with integrated 2 output LVDS fanout buffer and internal termination and is a member of the family of high performance clock solutions from IDT. The 889474 is optimized for high speed and very low output skew, making it suitable for use in demanding applications such as SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The internally terminated differential input and VREF_AC pins allow other differential signal families such as LVPECL, LVDS, LVHSTL and CML to be easily interfaced to the input with minimal use of external components. The 889474 is packaged in a small 4mm x 4mm 24-pin VFQFN package which makes it ideal for use in space-constrained applications.

Features

  • Two differential LVDS outputs
  • INx, nINx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, CML
  • 50? internal input termination to VT
  • Maximum output frequency: 2GHz (maximum)
  • Additive phase jitter, RMS: 0.06ps (typical)
  • Output skew: 20ps (maximum)
  • Propagation delay: 700ps (maximum)
  • 2.5V operating supply
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free RoHS-complaint package

Product Options

下单器件 ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
889474AKLF Active NLG24P1 VFQFPN 24 C Yes Tube
Availability
889474AKLFT Active NLG24P1 VFQFPN 24 C Yes Reel
Availability

技术资料

文档标题 他の言語 文档类型 文档格式 文件大小
数据手册与勘误表
889474 Final Data Sheet Datasheet PDF 205 KB
应用指南 &白皮书
AN-828 Termination - LVPECL Application Note PDF 229 KB
AN-846 Termination - LVDS Application Note PDF 50 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB
AN-815 Understanding Jitter Units Application Note PDF 476 KB
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB
PCN / PDN
PCN# : A1611-02 Add JCET China as Alternate Assembly and Change of Material Set at Alternate Assembly Location Product Change Notice PDF 583 KB
PCN# : TB1303-02 Change of Tape & Reel Packing Method for Selective Products Product Change Notice PDF 361 KB
其它
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB