NOTICE - The following device(s) are recommended alternatives:

The 854S036 is a low skew, high performance Dual Differential-to-LVDS Fanout Buffer. One of the two fanout buffers has 3 LVDS outputs, the other has 6 LVDS outputs. The PCLKx, nPCLKx pairs can accept most standard differential input levels. The 854S036 is characterized to operate from a 3.3V power supply. Guaranteed output and bank skew characteristics make the 854S036 ideal for those clock distribution applications demanding well defined performance and repeatability.

Features

  • Two independent differential LVDS output buffers, buffer A with three outputs, buffer B with 6 outputs
  • Two differential clock input pairs
  • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL
  • Output frequency: 2GHz
  • Translates any single ended input signal to LVDS levels with resistor bias on nPCLKx input
  • Output skew: 100ps (maximum)
  • Bank skew: 20ps (maximum)
  • Propagation delay: 550ps (maximum)
  • Additive phase jitter, RMS: 0.06ps (typical)
  • Full 3.3V power supply
  • 0°C to 70°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

Product Options

下单器件 ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
854S036AKLF Obsolete NLG32P1 VFQFPN 32 C Yes Tray
Availability
854S036AKLFT Obsolete NLG32P1 VFQFPN 32 C Yes Reel
Availability

技术资料

文档标题 他の言語 文档类型 文档格式 文件大小
数据手册与勘误表
ICS854S036 Datasheet Datasheet PDF 762 KB
应用指南 &白皮书
AN-828 Termination - LVPECL Application Note PDF 229 KB
AN-846 Termination - LVDS Application Note PDF 50 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB
AN-815 Understanding Jitter Units Application Note PDF 476 KB
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB
PCN / PDN
PDN# : CQ-17-04(R1) Product Discontinuance Notice Product Discontinuation Notice PDF 606 KB
PDN# : CQ-17-04 Product Discontinuance Notice Product Discontinuation Notice PDF 599 KB
PCN# : A1611-02 Add JCET China as Alternate Assembly and Change of Material Set at Alternate Assembly Location Product Change Notice PDF 583 KB
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB
其它
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Products for Radio Applications 日本語 Product Brief PDF 2.34 MB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB
IDT Fanout Buffers Product Overview Product Brief PDF 739 KB
High-Performance, Low-Phase Noise Clocks Buffers product brief Product Brief PDF 378 KB

软件与工具

文档标题 他の言語 文档类型 文档格式 文件大小
854S036 IBIS Model Model - IBIS ZIP 31 KB