NOTICE - The following device(s) are recommended alternatives:

The 8524 is a low skew, 1-to-22 Differential-to-HSTL Fanout Buffer . The 8524 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The device is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the OE pin. The 8524's low output and part-to-part skew characteristics make it ideal for workstation, server, and other high performance clock distribution applications.

Features

  • Twenty-two differential HSTL outputs each with the ability to drive 50? to ground
  • Selectable differential CLK, nCLK or LVPECL clock inputs
  • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, HSTL, SSTL, HCSL
  • PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL
  • Maximum output frequency: 500MHz
  • Translates any single-ended input signal (LVCMOS, LVTTL, GTL) to HSTL levels with resistor bias on nCLK input
  • Output skew: 80ps (maximum)
  • Part-to-part skew: 700ps (maximum)
  • Jitter, RMS: 0.04ps (typical)
  • LVPECL and HSTL mode operating voltage supply range: VDD = 3.3V ± 5%, VDDO = 1.6V to 2V, GND = 0V
  • 0°C to 85°C ambient operating temperature

Product Options

下单器件 ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
8524AYLF Obsolete EDG64P2 TQFP 64 C Yes Tray
Availability
8524AYLFT Obsolete EDG64P2 TQFP 64 C Yes Reel
Availability

技术资料

文档标题 他の言語 文档类型 文档格式 文件大小
数据手册与勘误表
8524 Datasheet Datasheet PDF 253 KB
应用指南 &白皮书
AN-828 Termination - LVPECL Application Note PDF 229 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB
AN-815 Understanding Jitter Units Application Note PDF 476 KB
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB
PCN / PDN
PDN# : CQ-17-04(R1) Product Discontinuance Notice Product Discontinuation Notice PDF 606 KB
PDN# : CQ-17-04 Product Discontinuance Notice Product Discontinuation Notice PDF 599 KB
PCN# : A1606-02 Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 567 KB
PCN# : TB1405-01 New Carrier Tape and Quantity per Reel Product Change Notice PDF 788 KB
PCN# : A1309-01 Changed of Traceability Mark Format Product Change Notice PDF 439 KB
其它
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB

软件与工具

文档标题 他の言語 文档类型 文档格式 文件大小
8524 IBIS Model Model - IBIS ZIP 45 KB