The 5T9306 2.5V differential clock buffer is a user-selectable differential input to six LVDS outputs. The fanout from a differential input to six LVDS outputs reduces loading on the preceding driver and provides an efficient clock distribution network. The 5T9306 can act as a translator from a differential HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be used to translate to LVDS outputs. The redundant input capability allows for an asynchronous change-over from a primary clock source to a secondary clock source. Selectable reference inputs are controlled by SEL. The 5T9306 outputs can be asynchronously enabled/disabled. When disabled, the outputs will drive to the value selected by the GL pin. Multiple power and grounds reduce noise.

Features

  • Guaranteed Low Skew < 25ps (max)
  • Very low duty cycle distortion < 125ps (max)
  • High speed propagation delay < 1.75ns (max)
  • Additive phase jitter, RMS 0.159ps (typical) @ 125MHz
  • Up to 1GHz operation
  • Selectable inputs
  • Hot insertable and over-voltage tolerant inputs
  • 3.3V / 2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input interface
  • Selectable differential inputs to six LVDS outputs
  • Power-down mode
  • 2.5V VDD
  • Available in VFQFPN package

Product Options

下单器件 ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
5T9306NLGI Active NLG28 VFQFPN 28 I Yes Tray
Availability
5T9306NLGI8 Active NLG28 VFQFPN 28 I Yes Reel
Availability

技术资料

文档标题 他の言語 文档类型 文档格式 文件大小
数据手册与勘误表
IDT5T9306 Data Sheet Datasheet PDF 159 KB
应用指南 &白皮书
AN-828 Termination - LVPECL Application Note PDF 229 KB
AN-846 Termination - LVDS Application Note PDF 50 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB
AN-815 Understanding Jitter Units Application Note PDF 476 KB
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB
PCN / PDN
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility Product Change Notice PDF 983 KB
PCN#: A-0410-02, Change IDT marking logo with new IDT gridless w Product Change Notice PDF 24 KB
PCN#: A-0412-04 - To comply with Pb-free labels - Green Products Product Change Notice PDF 80 KB
PCN#: L-0405-04 To comply with current EIA Std Product Change Notice PDF 143 KB
PCN#: A-0310-01, Green Products Product Change Notice PDF 26 KB
其它
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB
IDT Fanout Buffers Product Overview Product Brief PDF 739 KB
High-Performance, Low-Phase Noise Clocks Buffers product brief Product Brief PDF 378 KB

软件与工具

文档标题 他の言語 文档类型 文档格式 文件大小
5T9306 IBIS Model Model - IBIS ZIP 6 KB