The 553S is a low skew, single input to four output, LVCMOS clock buffer. The 553S has best in class additive phase Jitter of sub 50 fsec.

Features

  • Low additive phase jitter RMS: 50 fs
  • Extremely low skew outputs (50 ps)
  • Low cost clock buffer
  • Packaged in 8-pin SOIC and small 8-pin DFN package, Pb-free
  • Input / Output clock frequency up to 200 MHz
  • Ideal for networking clocks
  • Operating Voltages: 1.8 V to 3.3 V
  • Output Enable mode tri-states outputs
  • Advanced, low power CMOS process
  • Extended temperature range (-40°C to +105°C)

Product Options

下单器件 ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
553SCMGI Active CMG8 COL 8 I Yes Cut Tape
Availability
553SCMGI8 Active CMG8 COL 8 I Yes Reel
Availability
553SDCGI Active DCG8 SOIC 8 I Yes Tube
Availability
553SDCGI8 Active DCG8 SOIC 8 I Yes Reel
Availability

技术资料

文档标题 他の言語 文档类型 文档格式 文件大小
数据手册与勘误表
553S Datasheet Datasheet PDF 157 KB
应用指南 &白皮书
AN-845 Termination - LVCMOS Application Note PDF 62 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB
AN-815 Understanding Jitter Units Application Note PDF 476 KB
PCN / PDN
PCN# : A1905-02 Adding Carsem, Malaysia as Alternate Assembly Location & Change Material Sets Product Change Notice PDF 268 KB
PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB
PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB
其它
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB

软件与工具

文档标题 他の言語 文档类型 文档格式 文件大小
553S IBIS Model Model - IBIS ZIP 26 KB