The 552-02S is a low skew, single-input to eight-output clock buffer. The device offers a dual input with pin select for switching between two clock sources. It has best in class Additive Phase Jitter of sub 50 fsec.

Features

  • Low RMS Additive Phase Jitter: 50 fs
  • Low output skew: 50 ps
  • Operating voltages of 1.8 V to 3.3 V
  • Packaged in 16-pin TSSOP and 16-pin VFQFPN
  • Input clock multiplexer simplifies clock selection
  • Output Enable pin tri-states outputs
  • Input / Output clock frequency up to 200 MHz
  • Low power CMOS technology
  • 3.3 V tolerant inputs
  • Extended temperature (-40°C to +105°C)

Product Options

下单器件 ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
552-02SPGGI Active PGG16 TSSOP 16 I Yes Tube
Availability
552-02SPGGI8 Active PGG16 TSSOP 16 I Yes Reel
Availability
552-02SCMGI Active CMG16 COL 16 I Yes Cut Tape
Availability
552-02SCMGI8 Active CMG16 COL 16 I Yes Reel
Availability

技术资料

文档标题 他の言語 文档类型 文档格式 文件大小
数据手册与勘误表
552-02S Datasheet Datasheet PDF 242 KB
应用指南 &白皮书
AN-828 Termination - LVPECL Application Note PDF 229 KB
AN-845 Termination - LVCMOS Application Note PDF 62 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB
AN-815 Understanding Jitter Units Application Note PDF 476 KB
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB
其它
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB

软件与工具

文档标题 他の言語 文档类型 文档格式 文件大小
552-02S IBIS Model Model - IBIS ZIP 26 KB