NOTICE - The following device(s) are recommended alternatives:
9ZXL1950D - 19-Output DB1900ZL Low-Power Derivative
Pin-to-pin with improved performance
The 9ZXL1950 is a DB1900Z derivative buffer utilizing Low-Power HCSL (LP-HCSL) outputs to increase edge rates on long traces, reduce board space, and reduce power consumption more than 50% from the original 9ZX21901.It is pin-compatible to the 9ZXL1930 and fully integrates the output terminations. It is pin-compatible to the 9ZXL1930 and fully integrates the output terminations. It is suitable for PCI-Express Gen1/2/3 or QPI/UPI applications, and uses a fixed external feedback to maintain low drift for demanding QPI/UPI applications.

Features

  • 19 - LP-HCSL Differential Output Pairs w/integrated terminations (Zo = 85Ω)
  • LP-HCSL outputs; up to 90% IO power reduction, better signal integrity over long traces
  • Direct connect to 85Ω transmission lines; eliminates 76 termination resistors, saves 130mm² area
  • Pin compatible to the 9ZXL1930; easy upgrade to reduced board space
  • 72-VFQFPN package; smallest 19 output Z-buffer
  • Fixed feedback path; ~0ps input-to-output delay
  • 9 Selectable SMBus addresses; multiple devices can share same SMBus segment
  • Separate VDDIO for outputs; allows maximum power savings
  • PLL or bypass mode; PLL can dejitter incoming clock
  • 100MHz & 133.33MHz PLL mode; legacy QPI support
  • Selectable PLL BW; minimizes jitter peaking in downstream PLL's
  • Spread spectrum compatible; tracks spreading input clock for EMI reduction
  • SMBus Interface; unused outputs can be disabled

Product Options

下单器件 ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
9ZXL1950BKLF Active NLG72P1 VFQFPN 72 C Yes Tray
Availability
9ZXL1950BKLFT Active NLG72P1 VFQFPN 72 C Yes Reel
Availability

技术资料

文档标题 他の言語 文档类型 文档格式 文件大小
数据手册与勘误表
9ZXL1950 Datasheet Datasheet PDF 261 KB
应用指南 &白皮书
AN-975 Cascading PLLs Application Note PDF 128 KB
AN-828 Termination - LVPECL Application Note PDF 229 KB
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT's "Universal" Low-Power HCSL Outputs Application Note PDF 354 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB
AN-815 Understanding Jitter Units Application Note PDF 476 KB
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB
AN-808 PCI Express/HCSL Termination Application Note PDF 54 KB
PCN / PDN
PCN# : A1611-02 Add JCET China as Alternate Assembly and Change of Material Set at Alternate Assembly Location Product Change Notice PDF 583 KB
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB
PCN# : TB1504-01R1 Qty per Reel Standardization for Selective Packages Product Change Notice PDF 95 KB
PCN# : TB1504-01 Qty per Reel Standardization for Selective Packages Product Change Notice PDF 50 KB
PCN# : A1311-03R1 Alternate Assembly Locations Product Change Notice PDF 43 KB
PCN# : A1311-03 Alternate Assembly Locations Product Change Notice PDF 140 KB
PCN# : A1308-01 Add ASEK as Alternate Assembly for VFQFPN-72 Product Change Notice PDF 103 KB
PCN# : A1305-01 Gold Wire to Copper Wire Product Change Notice PDF 148 KB
其它
Timing Solutions Products Overview Overview PDF 4.11 MB
PCI Express® Timing Solutions Overview Overview PDF 301 KB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB

软件与工具

文档标题 他の言語 文档类型 文档格式 文件大小
9ZXL1950 IBIS Model Model - IBIS ZIP 50 KB