2:12 DB1200ZL Derivative Low Power HCSL Clock Mux

The 9ZML1253E is a second generation enhanced performance DB1200ZL derivative. The part is a pin-compatible
upgrade to the 9ZML1232B, while offering a much improved phase jitter performance. A fixed external feedback maintains low drift for critical QPI/UPI applications, while each input channel has software adjustable input-to-output delay to ease transport delay management for today's more complex server topologies. The 9ZML1253E has an SMBus Write Lockout pin for increased device and system security.

Features

  • SMBus write lock feature; increases system security
  • 2 software-configurable input-to-output delay lines; manage transport delay for complex topologies
  • LP-HCSL outputs with 85Ω Zout; eliminate 48 resistors, save 82mm² of area
  • 12 OE# pins; hardware control of each output
  • 3 selectable SMBus addresses; multiple devices can share same SMBus segment
  • Selectable PLL bandwidths; minimizes jitter peaking in cascaded PLL topologies
  • Hardware/SMBus control of PLL bandwidth and bypass; change mode without power cycle
  • Spread spectrum compatible; tracks spreading input clock for EMI reduction
  • 100MHz PLL Mode; UPI support
  • 10 x 10 mm 72-VFQFPN package; small board footprint

Product Options

下单器件 ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
9ZML1253EKILF Active NLG72P1 VFQFPN 72 I Yes Tray
Availability
9ZML1253EKILFT Active NLG72P1 VFQFPN 72 I Yes Reel
Availability

技术资料

文档标题 他の言語 文档类型 文档格式 文件大小
数据手册与勘误表
9ZML1233E_1253E Datasheet Datasheet PDF 314 KB 4月 12, 2018
应用指南 &白皮书
AN-1001 Combining PhiClock™ and 9ZXL1951D for PCIe Gen4/5 Application Note PDF 103 KB 3月 12, 2018
AN-975 Cascading PLLs Application Note PDF 128 KB 8月 2, 2017
AN-828 Termination - LVPECL Application Note PDF 229 KB 7月 5, 2016
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT's "Universal" Low-Power HCSL Outputs Application Note PDF 354 KB 12月 10, 2015
AN-879 Low-Power HCSL vs Traditional HCSL Application Note PDF 150 KB 4月 7, 2015
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB 5月 12, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB 5月 11, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB 5月 7, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB 4月 23, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB 4月 23, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB 1月 14, 2014
AN-808 PCI Express/HCSL Termination Application Note PDF 54 KB 1月 14, 2014
其它
Timing Solutions Products Overview Overview PDF 4.11 MB 10月 31, 2018
PCI Express® Timing Solutions Overview Overview PDF 301 KB 4月 19, 2018
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB 4月 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB 4月 24, 2016
软件与工具
9ZML1253E IBIS Model Model - IBIS ZIP 21 KB 5月 8, 2018

软件与工具

文档标题 他の言語 文档类型 文档格式 文件大小
9ZML1253E IBIS Model Model - IBIS ZIP 21 KB 5月 8, 2018

Evaluation Boards

Part Number Title 升序排列
EVK9ZXL1951D Evaluation Kit for 19-Output DB1900Z for PCIe Gen1-4 and QPI/UPI