The 9FGV0431 is a 4-output very low power clock generator for PCIe Gen 1–4 applications. The device has 4 output enables for clock management and supports 2 different spread spectrum levels in addition to spread off.

Features

  • 1.8V operation; reduced power consumption
  • OE# pins; support DIF power management
  • LP-HCSL differential clock outputs; reduced power and board space
  • Programmable slew rate for each output; allows tuning for various line lengths
  • Programmable output amplitude; allows tuning for various application environments
  • DIF outputs blocked until PLL is locked; clean system start-up
  • Selectable 0%, -0.25% or -0.5% spread on DIF outputs; reduces EMI
  • External 25MHz crystal; supports tight ppm with 0 ppm synthesis error
  • Configuration can be accomplished with strapping pins; SMBus interface not required for device control
  • 3.3V tolerant SMBus interface works with legacy controllers
  • Space-saving 5 x 5 mm 32-VFQFPN; minimal board space
  • Selectable SMBus addresses; multiple devices can easily share an SMBus segment

Product Options

下单器件 ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
9FGV0431AKILF Active NLG32P1 VFQFPN 32 I Yes Tray
Availability
9FGV0431AKILFT Active NLG32P1 VFQFPN 32 I Yes Reel
Availability
9FGV0431AKLF Active NLG32P1 VFQFPN 32 C Yes Tray
Availability
9FGV0431AKLFT Active NLG32P1 VFQFPN 32 C Yes Reel
Availability

技术资料

文档标题 他の言語 文档类型 文档格式 文件大小
数据手册与勘误表
9FGV0431 Datasheet Datasheet PDF 283 KB
应用指南 &白皮书
AN-975 Cascading PLLs Application Note PDF 128 KB
AN-918 Programmable Clocks vs Crystal Oscillators Application Note PDF 221 KB
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT's "Universal" Low-Power HCSL Outputs Application Note PDF 354 KB
AN-879 Low-Power HCSL vs Traditional HCSL Application Note PDF 150 KB
AN-843 PCI Express Reference Clock Requirements Application Note PDF 1.81 MB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB
AN-839 RMS Phase Jitter Application Note PDF 149 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB
AN-815 Understanding Jitter Units Application Note PDF 476 KB
AN-802 Crystal-Measuring Oscillator Negative Resistance Application Note PDF 52 KB
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB
PCN / PDN
PCN# : A1611-02 Add JCET China as Alternate Assembly and Change of Material Set at Alternate Assembly Location Product Change Notice PDF 583 KB
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB
其它
Timing Solutions Products Overview Overview PDF 4.11 MB
PCI Express® Timing Solutions Overview Overview PDF 301 KB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB
9FGV0431 Reference Schematic Schematic PDF 29 KB

软件与工具

文档标题 他の言語 文档类型 文档格式 文件大小
9FGV0431 IBIS Model Model - IBIS ZIP 93 KB