The 82P33910-1 Synchronization System for IEEE 1588 is comprised of software and hardware designed to meet the needs of IEEE 1588 slave clock and master clock applications. The system includes Precision Time Protocol (PTP) stack software (Stack) and clock recovery servo software (Servo) that runs on an external processor; and Synchronization Management Unit (SMU) hardware.

The included PTP stack is IEEE 1588-2008 compliant and is used to control the exchange of messages between IEEE 1588 masters and slaves. The Servo recovers accurate and stable electrical synchronization signals from packet based references generated by IEEE 1588 masters. The Servo is capable of filtering the effects of Packet Delay Variation (PDV) often present in IEEE 1588 unaware networks.

The SMU hardware provides tools to manage timing references, clock sources and timing paths for IEEE 1588 and Synchronous Ethernet (SyncE) based clocks. The device supports up to three independent timing paths that control: IEEE 1588 clock synthesis; SyncE clock generation; and general purpose frequency translation. The device supports physical layer timing with Digital PLLs (DPLLs) and it supports packet based timing with Digitally Controlled Oscillators (DCOs). Input-to-input, input-to-output and output-to-output phase skew can all be precisely managed. The device outputs low-jitter clocks that can directly synchronize Ethernet interfaces; as well as SONET/SDH and PDH interfaces and IEEE 1588 Time Stamp Units (TSUs).

For more information or to request documentation, please contact your local IDT sales representative.

Features

  • Includes IEEE 1588-2008 compliant protocol stack, clock recovery servo software, and Synchronization Management Unit (SMU) hardware
  • Implements ITU-T Telecom Profiles
  • Operates as IEEE 1588 / PTP slave or master
  • Recovers accurate and stable synchronization signals from packet based IEEE 1588 / PTP master
  • Reference trackers filter packet synchronization noise from IEEE 1588 unaware networks
  • PTP clocks comply with ITU-T G8273.2 and G.8263
  • Physical layer clocks comply with ITU-T G.8262 for Synchronous Ethernet Equipment Clock (EEC), and G.813 for Synchronous Equipment Clock (SEC), and Telcordia GR-253-CORE for Stratum 3 and SONET Minimum Clock (SMC)
  • System-wide precise 1PPS (Pulse Per Second) time of day alignment is supported with programmable input-to-input, input-to-output and output-to-output phase delays: sub-ns resolution
  • Generates clocks for: Ethernet, SONET/SDH and PDH interfaces: jitter generation <1 ps RMS (12 kHz to 20 MHz)
  • Eases local oscillator sourcing by supporting any of eight common TCXO/OCXO frequencies for the System Clock: 10 MHz, 12.8 MHz, 13 MHz, 19.44 MHz, 20 MHz, 24.576 MHz, 25 MHz or 30.72 MHz
  • 144 pin CABGA package

Product Options

下单器件 ID Part Status Pkg. Code Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
82P33910-1BAG Active BAG144 C Yes Tray
Availability
82P33910-1BAG8 Active BAG144 C Yes Reel
Availability

技术资料

文档标题 他の言語 文档类型 文档格式 文件大小
数据手册与勘误表
82P33910-1 Datasheet Datasheet PDF 119 KB 4月 5, 2017
使用指南与说明
Timing Commander Installation Guide Guide PDF 497 KB 10月 6, 2013
应用指南 &白皮书
AN-888 SMU for IEEE 1588 and Synchronous Ethernet 82P338xx/339xx Register Map Application Note PDF 666 KB 1月 25, 2017
AN-950 82P338XX/9XX Usage of a SYNC Input for Clock Alignment Application Note PDF 175 KB 11月 20, 2016
AN-807 Recommended Crystal Oscillators for NetSynchro WAN PLL Application Note PDF 77 KB 10月 27, 2016
AN-946 Using a 19.2MHz System Clock with 82P337xx/8xx/9xx Application Note PDF 165 KB 8月 22, 2016
AN-828 Termination - LVPECL Application Note PDF 229 KB 7月 5, 2016
AN-901 How to Implement Master/Slave for SETS and SMU Devices on Timing Redundancy Designs Application Note PDF 475 KB 7月 5, 2016
ITU-T Profiles for IEEE 1588 White Paper PDF 1.17 MB 10月 22, 2015
AN-846 Termination - LVDS Application Note PDF 50 KB 5月 12, 2014
AN-845 Termination - LVCMOS Application Note PDF 62 KB 5月 12, 2014
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB 5月 12, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB 5月 11, 2014
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB 5月 10, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB 5月 7, 2014
AN-839 RMS Phase Jitter Application Note PDF 149 KB 5月 6, 2014
AN-838 Peak-to-Peak Jitter Calculations Application Note PDF 32 KB 5月 6, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB 5月 5, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB 4月 23, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB 4月 23, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB 1月 14, 2014
AN-806 Power Supply Noise Rejection Application Note PDF 353 KB 1月 14, 2014
PCN / PDN
PCN# : A1702-01 Changed Mold Compound and Solder Paste on Select Packages Product Change Notice PDF 93 KB 5月 2, 2017
其它
Timing Solutions Products Overview Overview PDF 4.11 MB 10月 31, 2018
Timing Fabric for Next Generation Communications Equipment Overview ( 简体中文) English, 日本語 Overview PDF 1.31 MB 2月 21, 2017
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB 4月 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB 4月 24, 2016
Timing Fabric for Communications Equipment Overview Overview PDF 263 KB 12月 10, 2015
软件与工具
Timing Commander Installer (v1.13.1.21509) Software ZIP 20.40 MB 2月 14, 2019
82P33x10 Timing Commander Personality Software ZIP 3.61 MB 9月 11, 2017
82P33910-1 BSDL File Model - BSDL BSD 21 KB 1月 16, 2015

软件与工具

文档标题 他の言語 文档类型 文档格式 文件大小
Timing Commander Installer (v1.13.1.21509) Software ZIP 20.40 MB 2月 14, 2019
82P33x10 Timing Commander Personality Software ZIP 3.61 MB 9月 11, 2017
82P33910-1 BSDL File Model - BSDL BSD 21 KB 1月 16, 2015