The 9FGV1005 is a member of IDT's PhiClock™ programmable clock generator family. The 9FGV1005 provides two non-spread-spectrum copies of a single output frequency and one copy of the crystal reference input. Two select pins allow for hardware selection of the desired configuration, or two I2C bits allow easy software selection of the desired configuration. The user may configure any one of the four OTP configurations as the default when operating in I2C mode. Four unique I2C addresses are available, allowing easy I2C access to multiple components.

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diagram

Timing Commander Configuration File Upload (optional)

Use this form to upload your Timing Commander configuration file for the 9FGV1005 part. This will disable the configurator below. The datasheet addendum will be provided by IDT after review.

Configuration File (.tcs) Uploader

Global Configuration

Choose the number of configurations to program into the part. The 9FGV10xx will support up to four different configurations selectable using the SEL pins. Configurations
Default power up configuration when I2C is enabled. Any configuration number can be selected, even if it has not been factory programmed.” Default Configuration
Selects the I2C address of the device. Up to 4 addresses are supported, enabling using more than one 9FGV10xx on the same I2C bus. I2C Address
Programmable capacitance at XIN and XO (XIN in parallel with XO). Increment in steps of 0.5pf. Crystal Load Capacitance (pF)
Selects the desired integrated crystal reference frequency. Select 'None' if an external frequency reference will be used. Integrated Crystal Reference

Configuration 0

Input

Input frequency to the device. Valid range is 8 MHz-to-50 MHz for crystals and is 1MHz-to-240MHz for external clock generator. Input Frequency (MHz)
Single ended clock on crystal input (crystal overdrive)

Output

参数 REF0 OUT0 OUT1
Selects the default status of the output (on or off) at startup. This status can be modified in operation by I2C. Note: If REF0 is disabled, so is REF1. REF1 can be disabled without disabling REF0. 启用
Selects output type of the considered output. Available options are differential signalling (LVDS, LP-HCSL-100ohm or LP-HCSL-85ohm or LP-HCSL-33ohm which requires VDDO of 3.3 V) or single-ended (LVCMOS: first output of bank active, second output of bank active, or both outputs active either in phase or 180 degrees out of phase). Output Type
Selects output supply voltage and the signaling level for LVCMOS output types. VDDO
Output frequency. Valid range for integer output frequencies is 10 MHz-to-200 MHz for single-ended signaling and 10 MHz-to-325 MHz for differential signaling. Output Frequency (MHz)
Enables Spread Spectrum Modulation for the considered output(s). Spread Spectrum Enable
Specifies the Spread Spectrum modulation frequency. Valid range is 30-to-63 kHz. Spread Spectrum Modulation Freq. (kHz)

Configuration 1

Copy from Configuration 0

Input

Input frequency to the device. Valid range is 8 MHz-to-50 MHz for crystals and is 1MHz-to-240MHz for external clock generator. Input Frequency (MHz)
Single ended clock on crystal input (crystal overdrive)

Output

参数 REF0 OUT0 OUT1
Selects the default status of the output (on or off) at startup. This status can be modified in operation by I2C. Note: If REF0 is disabled, so is REF1. REF1 can be disabled without disabling REF0. 启用
Selects output type of the considered output. Available options are differential signalling (LVDS, LP-HCSL-100ohm or LP-HCSL-85ohm or LP-HCSL-33ohm which requires VDDO of 3.3 V) or single-ended (LVCMOS: first output of bank active, second output of bank active, or both outputs active either in phase or 180 degrees out of phase). Output Type
Selects output supply voltage and the signaling level for LVCMOS output types. VDDO
Output frequency. Valid range for integer output frequencies is 10 MHz-to-200 MHz for single-ended signaling and 10 MHz-to-325 MHz for differential signaling. Output Frequency (MHz)
Enables Spread Spectrum Modulation for the considered output(s). Spread Spectrum Enable
Specifies the Spread Spectrum modulation frequency. Valid range is 30-to-63 kHz. Spread Spectrum Modulation Freq. (kHz)

Configuration 2

Copy from Configuration 0

Input

Input frequency to the device. Valid range is 8 MHz-to-50 MHz for crystals and is 1MHz-to-240MHz for external clock generator. Input Frequency (MHz)
Single ended clock on crystal input (crystal overdrive)

Output

参数 REF0 OUT0 OUT1
Selects the default status of the output (on or off) at startup. This status can be modified in operation by I2C. Note: If REF0 is disabled, so is REF1. REF1 can be disabled without disabling REF0. 启用
Selects output type of the considered output. Available options are differential signalling (LVDS, LP-HCSL-100ohm or LP-HCSL-85ohm or LP-HCSL-33ohm which requires VDDO of 3.3 V) or single-ended (LVCMOS: first output of bank active, second output of bank active, or both outputs active either in phase or 180 degrees out of phase). Output Type
Selects output supply voltage and the signaling level for LVCMOS output types. VDDO
Output frequency. Valid range for integer output frequencies is 10 MHz-to-200 MHz for single-ended signaling and 10 MHz-to-325 MHz for differential signaling. Output Frequency (MHz)
Enables Spread Spectrum Modulation for the considered output(s). Spread Spectrum Enable
Specifies the Spread Spectrum modulation frequency. Valid range is 30-to-63 kHz. Spread Spectrum Modulation Freq. (kHz)

Configuration 3

Copy from Configuration 0

Input

Input frequency to the device. Valid range is 8 MHz-to-50 MHz for crystals and is 1MHz-to-240MHz for external clock generator. Input Frequency (MHz)
Single ended clock on crystal input (crystal overdrive)

Output

参数 REF0 OUT0 OUT1
Selects the default status of the output (on or off) at startup. This status can be modified in operation by I2C. Note: If REF0 is disabled, so is REF1. REF1 can be disabled without disabling REF0. 启用
Selects output type of the considered output. Available options are differential signalling (LVDS, LP-HCSL-100ohm or LP-HCSL-85ohm or LP-HCSL-33ohm which requires VDDO of 3.3 V) or single-ended (LVCMOS: first output of bank active, second output of bank active, or both outputs active either in phase or 180 degrees out of phase). Output Type
Selects output supply voltage and the signaling level for LVCMOS output types. VDDO
Output frequency. Valid range for integer output frequencies is 10 MHz-to-200 MHz for single-ended signaling and 10 MHz-to-325 MHz for differential signaling. Output Frequency (MHz)
Enables Spread Spectrum Modulation for the considered output(s). Spread Spectrum Enable
Specifies the Spread Spectrum modulation frequency. Valid range is 30-to-63 kHz. Spread Spectrum Modulation Freq. (kHz)

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